Method and apparatus for testing LCD panel array prior to shorting bar removal

ABSTRACT

Final testing of an LCD panel or the like is performed after preliminary testing for short circuit defects. During final testing, the panel is exposed to signals at the shorting bars and the resulting display pattern is imaged. The resulting image data then is processed at a computer system to determine whether the resulting display pattern differs from an expected display pattern. If differences are present then an open circuit or pixel defect is present. The applied test signals and the pattern or differences determine the type of defect present. For an open circuit defect along a gate line, a partial row (column) of the resulting display pattern does not activate. For an open circuit along a drive line, a partial column (row) of the resulting display does not activate. Pixel shorts are identified by applying test signals to the shorting bars during a first test cycle, then imaging the display during a second test cycle after at least one of the test signals is removed. Pixels which remain active that should be inactive have short circuit defects.

CROSS REFERENCE TO RELATED APPLICATION

This invention is related to commonly-assigned U.S. patent applicationSer. No. 07/557,257, filed July 24, 1990 of the same inventor for METHODAND APPARATUS FOR TESTING AN LCD PANEL ARRAY USING A MAGNETIC FIELDSENSOR.

BACKGROUND OF THE INVENTION

This invention relates to testing of liquid crystal display (LCD) panelarrays, and more particularly to a method and apparatus for testing LCDpanel arrays for open circuit and pixel defects by applying test signalsto panel shorting bars.

LCD panels typically are formed with a liquid crystal materialsandwiched between an active plate and a ground plate. Polarizers,colorizing filters and spacers also are included between the plates.During fabrication, many active plates panels may be formed on a singleglass plate. In each area of the glass plate which is to form an activeplate, panel, drive lines, gate lines and drive elements are formed.Typically, thin-film transistors are used for the drive elements.

Each active panel has an electro-static discharge (ESD) shorting bar ateach of the four edges of the active plate. The ESD bar shorts all thedrive lines or gate lines which terminate at a respective edge. For aninterdigitated panel, drive lines are terminated at two opposing edgeswhile gate lines are terminated at the other two edges. Thus, fourshorting bars are included, one per panel edge.

Until scribing and final testing of the LCD panel, the ESD bars remainattached to the panel so as to avoid electro-static charge buildup.Prolonged separation of the panel from the shorting bar or anothergrounding apparatus may cause the electro-static charge to accumulateand cause damage to the active panel circuitry. Accordingly, a method isneeded for testing the LCD panel array with the ESD shorting bars inplace.

Referring to FIG. 1, a typical active matrix LCD panel segment 10 isshown consisting of an array of pixels 12. Each pixel 12 is activated byaddressing simultaneously an appropriate drive line 14 and gate line 16.A drive element 18 is associated with each pixel 12. The drive lines 14,gate lines 16, pixels 12 and pixel drive elements 18 are deposited onthe clear glass “active” plate by a lithographic or similar process.Because of the high pixel densities, the close proximity of the gatelines and drive lines, and the complexity of forming the pixel driveelements, there is a significant probability of defects occurring duringthe manufacturing process.

Known testing methods for high density LCD panels include contacttesting methodologies which require connection to and testing of eachindividual row/column intersection within the panel array. For suchtesting, advanced probing technology is necessary to establish reliablecontacts among the densely populated pixel elements. A high density LCDarray includes 640 by 480 pixel elements per color. A typical test timefor such a panel is approximately 2 hours. For a color panel having thethree primary colors red green and blue (“RGB color panel”), a typicaltest cycle requires additional connections and requires additionaltesting time. The time and expense of testing, although necessary, is alimiting factor to the commercial success of large array LCD panels. Afaster and more efficient testing method is needed to reduce the testingcosts, and thereby reduce the product costs of LCD panels so as tocompete with CRT and other display types.

Accordingly, it is desirable to be able to test large arrays easily,without direct individual electrical connection and with connectionsonly as needed.

SUMMARY OF THE INVENTION

According to the invention, an LCD panel or the like is tested for opencircuit defects and pixel defects after preliminary short circuittesting is complete. According to one aspect of the invention, the panelundergoes open circuit and pixel testing by exposing the panel to testsignals at the contacts of each respective shorting bar. The resultingdisplay pattern then is imaged and compared to an expected displaypattern to detect panel defects.

According to another aspect of the invention, the resulting display isimaged of a TV camera, line-scan camera or other optical sensinginstrument. Such camera or instrument images the display panel andtransmits the resulting image signals to a computer system forprocessing and storage as sensed image data. The computer systemcompares the sensed image data to expected image data to determinewhether there are any differences between the resulting display patternand the expected display pattern.

As there are only a finite number of test patterns which may be appliedto the shorting bars, there are only a finite number of expected displaypatterns. By having the computer control or monitor the test signalselection, the computer is able to select the appropriate expecteddisplay pattern, and thus, select the appropriate expected image data tobe compared with the sensed image data.

According to another aspect of the invention, a pixel short circuitdefect is detected by applying sequential test cycles of test signals tothe shorting bars. During a first cycle, an active signal is applied tothe shorting bars which are connected to the gate lines, while anotheractive signal is applied to the shorting bars which are connected to thedrive lines. Then, during a second cycle, the active signal which isapplied to the drive lines is switched to an inactive signal. If anypixels remain active, then there is a pixel short circuit.Alternatively, the active signal applied to the gate lines may beswitched to an inactive state. Any pixels that become inactive resultfrom a pixel short circuit.

The invention will be better understood by reference to the followingdetailed description taken in conjunction with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a portion of an LCD panel array;

FIG. 2 is a block diagram of a test configuration for testing the LCDpanel of FIG. 1 according to an embodiment of this invention;

FIG. 3 is a block diagram of an LCD panel of FIG. 1 depicting an opencircuit defect;

FIGS. 4a-j are diagrams of expected display patterns in response torespective test signal combinations applied according to an embodimentof this invention; and

FIG. 5 is a flow chart for a test sequence according to an embodiment ofthis invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT Panel Configuration

Referring to FIG. 1, a section of an LCD panel 10 is shown includingseveral pixels 12. Associated with each pixel 12 is a drive line 14, agate line 16, and a drive element 18, as previously described. For aninterdigitated panel (shown), every other drive line is terminated alongone panel boundary 20, while the other drive lines are terminated alongthe opposite, but parallel, boundary 24 (see FIG. 2). Similarly, everyother gate line 16 is terminated along one panel boundary 22 adjacentand generally orthogonal to the drive line panel boundaries 20, 24,while the other gate lines 16 are terminated along the opposite panelboundary 26.

During final testing of the LCD panel 10, the electro-static dischargeshorting bars are present. As shown in FIGS. 1-3, there are fourshorting bars 28, 30, 32, 34 for an interdigitated panel, one at eachedge of the panel 10. Bar 28 shorts the drive lines 14 terminating atedge 20. Bar 30 shorts the gate lines 16 terminating at edge 22. Bar 32shorts the drive lines 14 terminating at edge 24. Bar 34 shorts the gatelines 16 terminating at edge 26.

For a high density monochrome LCD panel, the pixel array includes640×480 pixels (307,200 pixels). Each pixel corresponds to a singlearray element. By controlling the voltage levels of the test signalsapplied to shorting bars, the pixels are driven to correspond to white,black, or various gray levels in between.

For a high density RGB color panel there are three pixels for every onepixel of the monochrome panel. Thus, the RGB panel array includes640×480×3 pixels (921,600 pixels). By activating a combination of thethree pixels alternative colors are achieved for an array element. Byactivating all three pixels, a white color is achieved. According to oneembodiment of an RGB interdigitated panel, each color pixel correspondsto a separate element. Thus, the drive lines for the red, blue and greenpixels are connected to alternating shorting bars (28, 32), while thegate lines are also connected to alternate shorting bars (30,34).

Test Apparatus Configuration

Referring to FIG. 2, a test configuration 36 according to an embodimentof this invention is shown. The test configuration 36 includes the LCDpanel 10, a computer system 37, a conventional dc parametric measurementunit (PMU) 38, and a TV camera 39. During final testing, the PMU 38generates test signals applied to the shorting bars 28, 30, 32, 34,while the camera 39 images the resulting display pattern appearing onthe panel 10. The camera 39 generates image signals which are input tothe computer system 37 for processing to determine whether any defectsare present.

Preliminary Short Circuit Testing

Referring to FIG. 2, the test configuration 36 for detecting shortcircuit defects on an LCD panel 10 is shown. To detect whether the panel10 has any short circuit defects, a voltage signal is applied by the PMU38 to each shorting bar 28, 30, 32, 34, while also monitoring theshorting bars 28, 30, 32, 34. Alternatively, a voltage signal may beapplied to each one shorting bar in sequence while each of the othershorting bars are monitored. For example, bar 28 receives a voltagesignal while bars 30, 32, and 34 are monitored by the PMU 38. The PMU 38current sensor detect whether any current is flowing through the drivelines 14 and gate lines 16. If no current is detected by the PMU 38 atany of the shorting bars 28, 30, 32, 34, then the panel 10 has no shortcircuit defects and the panel is tested subsequently for open circuitdefects and defective pixels. If current is flowing at one or moreshorting bars, then a short circuit defect is present among the drivelines or gates lines terminating at such one or more shorting bars.

Upon completion of preliminary short circuit testing, the open circuittesting procedure is performed.

Test Signal Combinations for Open Circuit and Pixel Testing

To identify whether panel 10 has any open circuit or pixel defects,respective test signals are applied to shorting bars 28, 30, 32, 34.Under normal operation, a pixel 12 is addressed by applying an activesignal to the gate line 16 and drive line 14 connected to the driveelement 18 of the pixel 12. However, during testing the shorting bars28, 30, 32, 34 are connected to respective pluralities of drive lines orgate lines. As a result, individual pixels 12 can not be addressed. Foran interdigitated panel a combination of four test signals are appliedto generate an expected display pattern.

Table A below lists a set of test signal combinations, along withdescriptions of the expected display pattern corresponding to such testsignals:

TABLE A FIG. SB-28 SB-30 SB-32 SB-34 Expected Display 4a Black On BlackOn All pixels off 4b White On White On All pixels on 4c White On BlackOn Horizontal Stripes 4d Black On White On Inverse Horizontal Stripes 4eWhite Off White On Vertical Stripes 4f White On White Off InverseVertical Stripes 4g White On Black Off Checkerboard Cycle 1 4h Black OffWhite On Checkerboard Cycle 2 4i White Off Black On Inverse CheckerboardCy. 1 4j Black On White Off Inverse Checkerboard Cy. 2

SB-28, SB-30, SB-32, and SB-34 correspond respectively to shorting bars28, 30, 32 and 34. The test signals which are applied to the shortingbars 28, 32 are referred to as being “White” (e.g., logic high; active)or “Black” (e.g., logic low; inactive). The test signals which areapplied to the shorting bars 30, 34 are referred to as being “On” (e.g.,logic high; active) or “Off” (e.g., logic low; inactive). For achievinga gray level in a monochrome panel, intermediate voltage levels betweenthose for black and white are applied to the drive line shorting bars28, 32.

FIGS. 4a-j depict the expected display patterns listed in Table A for asmall portion (e.g., 4×4 pixels) of the panel array 10. FIG. 4a shows anexpected display pattern in which all pixels are inactive (e.g., dark).FIG. 4b shows an expected display pattern in which all the pixels areactive (e.g., white). FIG. 4c shows an expected display pattern in whichthe pixels form horizontal stripes. FIG. 4d shows an expected displaypattern in which the pixels form inverse horizontal stripes. FIG. 4eshows an expected display pattern in which the pixels form verticalstripes. FIG. 4f shows an expected display pattern in which the pixelsform inverse and vertical stripes. FIG. 4g shows test cycle 1 forgenerating an expected display pattern characterized as a checkerboardpattern. FIG. 4h shows test cycle 2 for generating the expected displaypattern characterized as a checkerboard pattern. FIG. 4i shows testcycle 1 for generating an expected display pattern characterized as aninverse checkerboard pattern. FIG. 4j shows test cycle 2 for generatingthe expected display pattern characterized as an inverse checkerboardpattern. For the patterns depicted in FIGS. 4e, 4f, 4g and 4i, the panel10 starts as being all dark. Thereafter, test signals are applied asshown to achieve the respective expected display pattern.

For an interdigitated monochrome panel, the striped and checkerboardexpected display pattern of FIGS. 4c-4j are embodied as alternatingwhite and black stripes or checker squares. For an interdigitated colorpanel, the striped and checkerboard expected display patterns of FIGS.4c-4j may appear to the human eye as alternating stripes of checkersquares of differing colors. The actual pattern, however, at the pixellevel is alternating dark and colored pixels.

Pixel Short Circuit Testing Procedure

According to the pixel short circuit testing procedure, short circuitsin the drive elements 18 and in the pixel elements 12 are detected. Eachdrive element 18, according to a preferred embodiment of the panel 10,is an FET transistor having a gate, a source and a drain. The gate iscoupled to a gate line 16. The source is coupled to a drive line 14. Thedrain is coupled to a pixel 12. Testing for cross shorts from gate tosource is performed during preliminary short circuit testing. Testingfor short circuits from gate to drain is done during either preliminaryshort circuit testing or final open circuit and pixel defect testing.

To detect a short circuit across the gate and drain of a drive element18, test signals are applied, for generating the all dark displaypattern of FIG. 4a. If any pixels 12 become active while such testsignals are applied there is a short circuit defect at the drive element18 of the active pixel 12.

To test for a short circuit in the pixel 12 itself, test signals areapplied during a first cycle which correspond to the fully active (e.g.all white) display pattern of FIG. 4b. Next, during a second test cycle,the test signals at shorting bars 30, 34 are switched off. If any pixelsremain active, then such pixels have a short circuit defect.

Open Circuit Defect Testing

To test for open circuit defects, one or more of the test signalcombinations in Table A (other than the “all pixels off” test signalcombination) are applied to the shorting bars 28, 30, 32, 34 to generatea resulting display pattern. If an open circuit defect is present, theresulting display varies from the corresponding expected displaypattern. For example, an open circuit along a drive line 14 causes allpixels 12 coupled to the drive line 14 beyond the open circuit not to beactivated. As a result, for a fully active expected display pattern(FIG. 4b), a line segment of inactive pixels 12 appears where activepixels 12 should appear.

FIG. 3 depicts an open circuit defect 52 on a drive line 14e. Pixels 54to the left of the open circuit defect 52 receive the test signalapplied along drive line 14e (from shorting bar 28). Pixels 56 to theright of the open circuit defect 52 are unable to receive the testsignal along line 14e. Thus, such pixels 56 do not become active.

According to alternative embodiments, test signals are applied to theshorting bars 28, 30, 32, 34 in one or more of the combinations listedin Table A. According to a preferred embodiment, test signals areapplied corresponding to the expected display pattern of FIG. 4b (allpixels active). If any pixels are not lit, then there is an open circuitpixel defect. If the inactive pixels form a line segment as describedfor FIG. 3, then there is an open circuit in the corresponding driveline or gate line. If the inactive pixels occur in isolated locations(e.g. not in a line segment) then there are open circuits at each of theinactive pixels.

Imaging and Processing of the Resulting Display Pattern

For both open circuit testing and pixel defect testing, a resultingdisplay pattern corresponds to an expected display pattern when thereare no defects present. If however, the resulting display pattern doesnot correspond to the expected display pattern, then a defect ispresent.

According to a preferred embodiment, the resulting display is imaged atTV camera 39 and sent to the computer system 37 for processing.Typically, the TV camera 39 generates analog video signals. The analogsignals are then converted to digital image signals by an Analog toDigital converter (not shown) at either the camera 39, the computersystem 37 or between the camera 39 and the computer system 37. Thedigital sensed image data then is processed at computer system 37 bycomparing the sensed image data to expected image data. The expectedimage data is determined according to the expected display pattern.

A resulting display pattern is imaged by the TV camera 39 while testsignals are applied to the shorting bars 28, 30, 32 and 34. Resultingimage signals are converted to digital image data, then processed andstored at the computer system 37. The computer 37 processes the sensedimage data to determine whether the resulting display patterncorresponds to the expected display pattern. The computer 37 identifieswhich sensed image data differs from the expected image data to locatethe differences between the resulting and the expected display patterns.

FIG. 5 is a flow chart for implementing a final test for open circuitand pixel defect testing according to one embodiment of this invention.First at step 60, a test sequence is retrieved (i.e., a standardsequence stored in memory or a sequence as defined by an operator). Thenat step 62, the first test is performed by signalling the PMU 38 toapply test signals to shorting bars 28, 30, 32, 34. At step 64, thecomputer system 37 signals the camera 39 to image the panel 10. Thecamera then images the resulting display pattern and sends the sensedimage data to the computer system 37. At step 66, the computer waits forsensed image data to be received. The computer system 37 then comparesat step 68 the sensed image data to predefined expected image datastored in memory. The expected image data used for comparison isdetermined according to the particular test being implemented. If anydifferences are present among the data comparisons, then the panel array10 has a defect. The computer system identifies the location of eachmismatch at step 70. Additional processing may be done to process thedifferences and identify a line segment (and thus an open circuit driveline or gate line) or an individual pixel (and thus an open circuitpixel defect, or for an all dark expected display, a short circuit pixelor pixel drive element defect). At step 72, another test is started.

According to one example, three different tests are performed. First,test signals are applied corresponding to the all dark pattern of FIG.4a. Any differences from the expected display correspond to shortcircuit pixel drive elements. Second, test signals are appliedcorresponding to the all active expected display pattern of FIG. 4b. Anydifferences from the expected display pattern correspond to an opencircuit drive line, gate line, or pixel depending on the pattern of thedifferences. Third, a two cycle test in which test signals are appliedcorresponding to the all active expected display pattern of FIG. 4bduring a first cycle, following by a second cycle during which the drivelines are deactivated. The expected display after the second cycle isthe all dark display pattern. Any differences correspond to a shortcircuit in the active pixel(s).

Other tests also may be performed in which test signals corresponding toother expected display patterns (i.e., those in FIGS. 4c-4j or otherpatterns from test signal combinations not explicitly described) areapplied.

Sensed Image Data Groups

The TV camera 39 or other optical sensing instrument used to image theresulting display pattern, in effect, scans the panel array 10 or aportion of the panel array 10. The TV camera 39 resolution or digitalsampling may correspond to the panel pixels on a one to one basis or onan ‘n’ to one basis where ‘n’ is greater than one. Typically, a group ofsensed image data corresponds to one pixel. Thus, a group size for thesensed image data may be one (e.g., one memory data item per pixel) orlarger (e.g., several memory data items per pixel). For a grouping ofseveral data items per pixel, all the data items corresponding to onepixel are summed to generate a value corresponding to the luminousintensity of the pixel. Each intensity sums is compared to specificationlimits for the LCD panel array according to whether the test signalsapplied correspond a dark pixel, a white pixel or some intermediate graylevel pixel. Accordingly, gray scale testing also may be performed aspart of the comparison with the expected display pattern data. For acolor panel, not only the intensity, but the color of each pixel also iscompared.

Conclusion

Although a preferred embodiment of the invention has been illustratedand described, various alternatives, modifications and equivalents maybe used. For example, although a TV camera 39 is described as theapparatus for imaging the display panel, a video camera, line-scancamera or other optical sensing instrument may used instead. Therefore,the foregoing description should not be taken as limiting the scope ofthe invention which is defined by the appended claims.

What is claimed is:
 1. A method for testing an LCD panel having aplurality of drive lines oriented in a first direction and a pluralityof gate lines oriented in a second generally orthogonal directioncreating row/column intersections, each drive line which terminatesalong a first edge of the panel being shorted together by a firstshorting means, each gate line which terminates along a second edge ofthe panel being shorted together by a second shorting means, said methodcomprising the steps: applying a first test signal to said firstshorting means and a second test signal to said second shorting means togenerate a first resulting display pattern; comparing said firstresulting display pattern to an expected display pattern, a differencebetween the resulting display pattern and the expected display patternsignifying that the panel has a defect.
 2. The method of claim 1,further comprising the step of imaging a portion of said first resultingdisplay pattern to generate sensed image data; wherein said expecteddisplay pattern comprises expected image data; and wherein said step ofcomparing comprises processing said sensed image data by comparing saidsensed image data to expected image data, a difference between sensedimage data and expected image data resulting from a panel defect.
 3. Amethod for testing an LCD panel having a plurality of drive linesoriented in a first direction and a plurality of gate lines oriented ina second generally orthogonal direction creating row/columnintersections, each drive line which terminates along a first edge ofthe panel being shorted together by a first shorting means, each driveline which terminates along a second opposing edge of the panel beingshorted together by a second first shorting means, each gate line whichterminates along a third edge of the panel being shorted together by athird shorting means, each gate line which terminates along a fourthedge of the panel being shorted together by a fourth shorting means,said method comprising the steps: applying a first test signal to saidfirst shorting means, a second test signal to said second shortingmeans, a third test signal to said third shorting means and a fourthtest signal to said fourth shorting means to generate a resultingdisplay pattern; comparing said resulting display pattern to an expecteddisplay pattern, a difference between the resulting display pattern andthe expected display pattern signifying that the panel has a defect. 4.The method of claim 3, further comprising the step of imaging a portionof said resulting display pattern to generate sensed image data; whereinsaid expected display pattern comprises expected image data; and whereinsaid step of comparing comprises processing said sensed image data bycomparing said sensed image data to expected image data, a differencebetween sensed image data and expected image data resulting from a paneldefect.
 5. An apparatus for testing an LCD panel, the panel having aplurality of drive lines oriented in a first direction and a pluralityof gate lines oriented in a second generally orthogonal directioncreating row/column intersections, each drive line which terminatesalong a first edge of the panel being shorted together by a firstshorting means, each gate line which terminates along a second edge ofthe panel being shorted together by a second shorting means, saidapparatus comprising: means for applying a first test signal to saidfirst shorting means and for applying a second test signal to saidsecond shorting means to generate a resulting display pattern; means forimaging the resulting display pattern to generate sensed image data;means for comparing the sensed image data to expected image data, adifference between the sensed image data and the expected image datasignifying that the panel has a defect.
 6. The apparatus of claim 5, inwhich the panel is an interdigitated panel having another plurality ofdrive lines which are shorted together by a third shorting means andanother plurality of gate lines which are shorted by a fourth shortingmeans; in which said applying means also is for applying a third testsignal to the third shorting means and a fourth test signal to thefourth shorting means to generate said resulting display pattern.
 7. Theapparatus of claim 6, in which said first test signal and said thirdtest signal are inactive, and said second test signal and said fourthtest signal are active, and wherein a difference between sensed imagedata and expected image data signifies a pixel short circuit defect. 8.The apparatus of claim 6, in which said first, second, third and fourthtest signals are active, and wherein a difference between sensed imagedata and expected image data signifies that the panel has an opencircuit defect.
 9. The apparatus of claim 6, in which said first,second, third and fourth test signals are active during a first testcycle, said first and third test signals being switched to inactiveduring a second test cycle, wherein a difference between sensed imagedata and expected image data during said second test cycle signifiesthat the panel has a short circuit.
 10. The method of claim 2 whereinsaid imaging step comprises imaging said portion of said first resultingdisplay pattern using an optical sensing instrument to generate saidsensed image data.
 11. The method of claim 10 wherein said opticalsensing instrument is a television camera.
 12. The method of claim 10wherein said optical sensing instrument is a video camera.
 13. Themethod of claim 10 wherein said optical sensing instrument is aline-scan camera.
 14. The method of claim 1 further comprising imaging aportion of said first resulting display pattern to generate an expecteddisplay pattern using a sensing instrument.
 15. The method of claim 14wherein the sensing instrument comprises a video camera.
 16. The methodof claim 14 wherein the sensing instrument comprises a televisioncamera.
 17. The method of claim 14 wherein the sensing instrumentcomprises a line-scan camera.
 18. The method of claim 4 wherein saidimaging step comprises imaging said portion of said resulting displaypattern using an optical sensing instrument to generate said sensedimage data.
 19. The method of claim 18 wherein said optical sensinginstrument is a video camera.
 20. The method of claim 18 wherein saidoptical sensing instrument is a television camera.
 21. The method ofclaim 18 wherein said optical sensing instrument is a line-scan camera.22. The apparatus of claim 5, wherein said means for imaging comprises asensing instrument.
 23. The apparatus of claim 22 wherein the sensinginstrument is an optical sensing instrument.
 24. The apparatus of claim22 wherein said optical sensing instrument is selected from a televisionor video camera or a line-scan camera.
 25. The method of claim 3 whereinthe expected display pattern is for an all pixels turned off logicstate.
 26. The method of claim 3 wherein the expected display pattern isfor an all pixels turned on logic state.
 27. The method of claim 3wherein the expected display pattern is for a horizontal stripes logicstate.
 28. The method of claim 3 wherein the expected display pattern isfor an inverse horizontal stripes logic state.
 29. The method of claim 3wherein the expected display pattern is for a checkerboard cycle 1 logicstate.
 30. The method of claim 3 wherein the expected display pattern isfor a checkerboard cycle 2 logic state.
 31. The method of claim 3wherein the expected display pattern is for an inverse checkerboardcycle 1 logic state.
 32. The method of claim 3 wherein the expecteddisplay pattern is for an inverse checkerboard cycle 2 logic state. 33.The method of claim 1 wherein the first test signal and the second testsignal are provided at an intermediary voltage to create a mid-levellogic state.
 34. The method of claim 1 wherein the defect is a shortcircuit.
 35. The method of claim 1 wherein the defect is an opencircuit.
 36. The method of claim 1 wherein said LCD panel comprises anarray of pixels.
 37. The method of claim 1 wherein said LCD panel iscomposed of a portion of a plate.
 38. The method of claim 3 wherein saidLCD panel comprises an array of pixels.
 39. The method of claim 3wherein said LCD panel is composed of a portion of a plate.
 40. Theapparatus of claim 5 wherein said LCD panel comprises an array ofpixels.
 41. The apparatus of claim 5 wherein said LCD panel is composedof a plate.
 42. The method of claim 1 wherein said testing method of theLCD panel is performed on a first plate having said plurality of drivelines and said plurality of gate lines.
 43. The method of claim 42further comprising imaging a portion of said first resulting displaypattern to generate an expected display pattern using a sensinginstrument.
 44. The method of claim 1 wherein said testing method of theLCD panel is performed on a first plate having said plurality of drivelines and said plurality of gate lines, and a plurality of transistors,where each of the transistors is coupled between at least one drive lineand at least one gate line.
 45. The method of claim 44 furthercomprising imaging a portion of said first resulting display pattern togenerate an expected display pattern using a sensing instrument.
 46. Themethod of claim 45 wherein the sensing instrument is selected from avideo camera, a line scan camera, or a television camera.
 47. The methodof claim 1 wherein said testing method of the LCD panel is performed ona portion of a first plate having said plurality of drive lines and saidplurality of gate lines, and a plurality of transistors, where each ofthe transistors is coupled between at least one drive line and at leastone gate line, the first plate further comprising a plurality ofcapacitors, where each of the capacitors is coupled to one of thetransistors.
 48. The method of claim 47 further comprising imaging aportion of said first resulting display pattern to generate an expecteddisplay pattern using a sensing instrument.
 49. The method of claim 1wherein said testing method of the LCD panel is performed on a portionof first plate having said plurality of drive lines and said pluralityof gate lines, and a plurality of transistors, where each of thetransistors is coupled between at least one drive line and at least onegate line, the first plate further comprising a plurality of capacitors,where each of the capacitors is coupled to one of the transistors, thefirst plate being coupled to a second plate having a color filtercoupled thereto, and a liquid crystal display material sandwichedbetween said first and second plates.
 50. The method of claim 49 furthercomprising imaging a portion of said first resulting display pattern togenerate an expected display pattern using a sensing instrument.
 51. Themethod of claim 50 wherein the sensing instrument is selected from avideo camera, a line scan camera, or a television camera.
 52. The methodof claim 1 wherein said testing method of the LCD signal is performed ona portion of a first plate having said plurality of drive lines and saidplurality of gate lines, and a plurality of transistors, where each ofthe transistors is coupled between at least one drive line and at leastone gate line, the first plate further comprising a plurality ofcapacitors, where each of the capacitors is coupled to one of thetransistors, the first plate being coupled to a second plate through aliquid crystal display material sandwiched between said first and secondplates.
 53. The method of claim 52 further comprising imaging a portionof said first resulting display pattern to generate an expected displaypattern using a sensing instrument.
 54. The method of claim 53 whereinthe sensing instrument is selected from a video camera, a line scancamera, or a television camera.
 55. The method of claim 3 wherein saidtesting method of the LCD panel is performed on a portion of a firstplate having said plurality of drive lines and said plurality of gatelines.
 56. The method of claim 3 wherein said testing method of the LCDpanel is performed on a portion of a first plate having said pluralityof drive lines and said plurality of gate lines, and a plurality oftransistors, where each of the transistors is coupled between at leastone drive line and at least one gate line.
 57. The method of claim 3wherein said testing method of the LCD panel is performed on a portionof a first plate having said plurality of drive lines and said pluralityof gate lines, and a plurality of transistors, where each of thetransistors is coupled between at least one drive line and at least onegate line, the first plate further comprising a plurality of capacitors,where each of the capacitors is coupled to one of the transistors. 58.The method of claim 3 wherein said testing method of the LCD panel isperformed on a portion of a first plate having said plurality of drivelines and said plurality of gate lines, and a plurality of transistors,where each of the transistors is coupled between at least one drive lineand at least one gate line, the first plate further comprising aplurality of capacitors, where each of the capacitors is coupled to oneof the transistors, the first plate being coupled to a second platehaving a color filter coupled thereto, and a liquid crystal displaymaterial sandwiched between said first and second plates.
 59. The methodof claim 3 wherein said testing method of the LCD panel is performed ona portion of a first plate having said plurality of drive lines and saidplurality of gate lines, and a plurality of transistors, where each ofthe transistors is coupled between at least one drive line and at leastone gate line, the first plate further comprising a plurality ofcapacitors, where each of the capacitors is coupled to one of thetransistors, the first plate being coupled to a second plate through aliquid crystal display material sandwiched between said first and secondplates.
 60. The apparatus of claim 5 wherein said testing method of theLCD panel is performed on a portion of a first plate having saidplurality of drive lines and said plurality of gate lines.
 61. Theapparatus of claim 5 wherein said testing method of the LCD panel isperformed on a portion of a first plate having said plurality of drivelines and said plurality of gate lines, and a plurality of transistors,where each of the transistors is coupled between at least one drive lineand at least one gate line.
 62. The apparatus of claim 5 wherein saidtesting method of the LCD panel is performed on a portion of a firstplate having said plurality of drive lines and said plurality of gatelines, and a plurality of transistors, where each of the transistors iscoupled between at least one drive line and at least one gate line, thefirst plate further comprising a plurality of capacitors, where each ofthe capacitors is coupled to one of the transistors.
 63. The apparatusof claim 5 wherein said testing method of the LCD panel is performed ona portion of a first plate having said plurality of drive lines and saidplurality of gate lines, and a plurality of transistors, where each ofthe transistors is coupled between at least one drive line and at leastone gate line, the first plate further comprising a plurality ofcapacitors, where each of the capacitors is coupled to one of thetransistors, the first plate being coupled to a second plate having acolor filter coupled thereto, and a liquid crystal display materialsandwiched between said first and second plates.
 64. The apparatus ofclaim 5 wherein said testing method of the LCD panel is performed on aportion of a first plate having said plurality of drive lines and saidplurality of gate lines, and a plurality of transistors, where each ofthe transistors is coupled between at least one drive line and at leastone gate line, the first plate further comprising a plurality ofcapacitors, where each of the capacitors is coupled to one of thetransistors, the first plate being coupled to a second plate through aliquid crystal display material sandwiched between said first and secondplates.